Conventionally, there is a technique for reducing the occupancy area of a semiconductor device by laminating chips in a multi-layered state, where the chips includes semiconductor elements and/or integrated circuits formed on respective substrates. The laminated chips are electrically connected to each other by through-electrodes, each of which is formed of metal embedded in a through-hole penetrating a substrate.
In general, embedding of metal in a through-hole is performed by means of electrolytic plating. As electrolytic plating of this kind, for example, there is bottom-up plating that gradually deposits the metal from the closed bottom of the through-hole to the opening, and there is conformal plating that deposits the metal from the entire inner peripheral surface of the through-hole.
The conformal plating is more advantageous in that it can complete embedding of the metal in the through-hole in a shorter time, as compared with the bottom-up plating. According to such conformal plating, electric field concentration is caused at the opening end portion of the through-hole, and so the deposition rate of the metal is higher at the opening end portion than at the inner peripheral surface of the through-hole. Consequently, there may be a case where a void is formed inside the metal embedded in the through-hole.